A semiconductor device is structured such that, for example, above a semiconductor substrate having a semiconductor element such as a CMIS (Complementary Metal Insulator Semiconductor) FET formed thereon, a multilayer wiring is formed by a metal film mainly made of, for example, Cu (copper) or Al (aluminum) and that a final passivation film is formed above the multilayer wiring.
Japanese Patent Application Publication Laid-Open No. 2001-53075 (Patent Document 1) discloses a structure shown in FIG. 3 in which a wire 22 serving as an external terminal is connected to a wiring layer 17 having the surface coated with a nickel/gold or nickel/palladium coating layer 18.
Japanese Patent Application Publication Laid-Open No. 2003-218278 (Patent Document 2) discloses a structure described in the summary in which a rewiring conductor has an external electrode 6 formed thereon, which is almost pillar-like and has a stress relaxing function.
Japanese Patent Application Publication Laid-Open No. 2007-158043 (Patent Document 3) discloses a structure shown in FIG. 3 in which a wiring 16 connected to a first electrode 11 is extended over a stress relaxing layer 15, on which an external terminal 12 formed as a solder ball is connected to the wiring 16.
Japanese Patent Application Publication Laid-Open No. 2012-4210 (Patent Document 4) discloses a structure shown in FIG. 25 in which a pad 18 composed of an Ni film 18a and an Au film 18b that are stacked together is disposed on the surface of a rewiring 15 and is connected to a wire 20.